Fail data is critical to verify device under test (“DUT”) functionality. Fail data test results can be analyzed and provide information that can be used to repair the DUT by using spare elements or decide whether the device is useful or not. As device density increases, it is very important to achieve test time performance in a production environment.
Within traditional testing architectures, conventional solutions often assign fixed sizes of buffer memory to each DUT to capture its respective fail data. As such, modern testing hardware often uses DMA (direct memory access) mechanisms to store fail data in a memory buffer of a fixed sized that is assigned to a particular a DUT. Thus, when a predefined memory threshold has been reached by a DUT's corresponding memory buffer, the testing hardware generally halts further receipt of fail data from the DUT to process the data. Accordingly, the testing hardware then waits for the data processor to process the fail data stored in the memory buffer before it can send more fail data from the DUT to its corresponding memory buffer.
Thus, the constraints imposed by conventional solutions assigning fixed size buffers often fail to account for different DUTs having different sizes of fail data. In general, fail data is not evenly distributed on all DUTs which can result in some DUTs having significantly more fail data than other DUTs. Accordingly, solutions that require even-memory allocation across DUTs do not provide an efficient means to use test memory resources.
Moreover, conventional solutions for assigning fixed size buffers often have difficulty determining how to set a fixed size threshold for buffers. For instance, if a buffer size threshold is set to a value that is too large and a buffer is full, it will take a long time to process the buffer which can result in processing inefficiencies and memory inefficiencies by allocating too much unused buffer space to the DUTs. If a buffer size threshold is set to a value that is too small, too many interrupts get generated which can cause processing inefficiency due to the overhead needed to process the interrupts. As a result, DMA engines processing fail data stored in the buffers have to pause/resume too many times, which can negatively impact testing performance.